In the field of semiconductor device manufacturing, active semiconductor devices such as, for example, transistors are generally manufactured or fabricated through processes commonly known as front end of line (FEOL) technologies. A transistor may be, for example, a field-effect-transistor (FET) and may be more specifically a complementary metal-oxide-semiconductor (CMOS) FET. A FET may also be a p-type dopant doped PFET or an n-type dopant doped NFET. Recently, high-k metal gate (HKMG) semiconductor transistors have been introduced because of their superior performance over conventional poly-based CMOS-FET. In addition, a replacement metal gate (RMG) process has been developed to further enhance the performance of HKMG transistors.
It is generally known that performance of a transistor may be greatly improved by introducing stresses in the channel region of the transistor. This is mainly because stresses increase the mobility of carriers, either holes or electrons depending on the type of the transistor, thereby increasing the response speed of the transistor. There are many different approaches of applying stresses to the channel of a transistor. For example, a compressive or tensile stress liner may be applied to the top of the transistor which may convey the stress through the gate and surrounding areas to the channel. Alternatively, appropriate types of stressors may be formed or embedded in the source and drain regions of a transistor that apply stresses toward the channel in-between the source and drain regions.
In forming source and drain with embedded stressors, recesses are normally first created in the source and drain regions, followed by epitaxial growth of silicon-germanium (SiGe) for pFET and silicon-carbide (SiC) for nFET transistors. With the continuous scaling down of real estate for semiconductor devices, real estate for the source/drain regions become extremely small and/or narrow and often closely surrounded by shallow trench isolation (STI) regions.